Exemplary embodiments of the present invention relate to semiconductor technologies, and more particularly, to a semiconductor device including an inner interconnection structure.
A semiconductor device package requires semiconductor chips to be mounted at a high density in a small area. Therefore, what is being developed is a technology for forming a three-dimensional stack package by contacting semiconductor chips using a through silicon via (TSV) structure. Because the TSV is formed to pierce a semiconductor chip, the TSV structure can reduce an electrical signal transmission path more effectively than a wire bonding structure. Thus, the TSV structure is expected to be advantageous to high-speed operation devices.
Because the TSV is introduced to pierce the semiconductor chip, the TSV is located in a restricted region on the surface of the semiconductor chip. Although the TSV cannot be disposed in an active region of the semiconductor chip in which circuit elements are integrated, the TSV may be located in an edge region of the semiconductor chip or in a center region of the semiconductor chip in which a scribe lane region is located. Thus, the exposure location of a TSV exposed as a connection terminal on the rear surface of the semiconductor chip is restricted within the restricted region.
Solder balls may be used when mounting a semiconductor chip on a module substrate or another electronic device as external connection terminals for the electrical connection between the semiconductor chip and the module substrate or another electronic device. However, the arrangement of solder balls is restricted by the JEDEC (Joint Electron Device Engineering Council) standards, and the location of the solder ball may be inconsistent with the location of a TSV. Thus, in order to electrically connect the solder ball and the TSV, a printed circuit board (PCB) or a rearrangement interconnection for interconnection routing is disposed between the solder ball and the semiconductor chip. Thus, the location of the TSV may be restricted by the arrangement of solder balls, and the electrical signal path may be increased by the introduction of a separate substrate.